The present invention relates to manufacturing methods for a high-breakdown-voltage, high-power vertical insulated-gate semiconductor device and rectification element (diode). More specifically, the invention relates to an IGBT and a MOSFET having an insulating film formed on the surface of a semiconductor layer or in trenches and a control electrode formed on the insulating film, a pn junction diode not having such a control electrode, and like devices.
To satisfy the recent requirements of miniaturization and enhanced performance of power source equipment in the power electronics field, efforts have been made in a concentrated manner to improve the performance, more specifically, to increase the breakdown voltage, increase the current, decrease the loss, increase the breakdown resistance, and increase the operation speed, in power semiconductor devices used in such power source equipment. In medium to high breakdown voltage range of 600 V to 6,500 V, insulated-gate bipolar transistors (hereinafter abbreviated as IGBTs) are the mainstream of power semiconductor devices. In IGBTs in the breakdown voltage range of 600 V to 1,700 V, remarkable improvements have been made in breakdown voltage among the above-mentioned various characteristics. The wafer thinning technique is a major technique that supports such improvements in the characteristics of IGBTs.
A device wafer process of the wafer thinning technique is as follows. First, a main device structure is formed on an FZ high-resistivity n− silicon wafer. At a stage that is close to a final step of device formation, the wafer is ground from its back side to such a thickness that a necessary device breakdown voltage can be secured and a sufficiently low loss characteristic can be obtained. A shallow p-type collector layer and a deep n-type layer are formed by implanting impurity ions through the thus-ground wafer back surface and a metal electrode is contact-formed on the back surface. (T. Laska et al., “The Field Stop IGBT (FS IGBT)—A New Power Device Concept with a Great Improvement Potential,” IEEE ISPSD 2000, pp. 355-358)
However, to secure a necessary device breakdown voltage and attain a low-loss characteristic, the wafer thickness after grinding is about 60 to 70 μm in devices having a breakdown voltage of 600 V and has a very small value of 100 μm+α in devices having a breakdown voltage of 1,200 V. If an 8-inch wafer, for example, having such a small thickness is handled and subjected to ion implantation and electrode formation from the back side, there is a very high probability that the wafer is broken during that course of processing. Accordingly, productivity cannot be increased easily. Furthermore, since ion implantation and activation are performed from the wafer front side at a stage that is after formation of a main device structure on the wafer front surface and close to a final step, the activation anneal temperature is restricted to 600° C. or less. This makes it difficult to control the impurity concentrations and the thicknesses of the p-type collector layer and the low-resistivity n-type layer.
On the other hand, the manufacturing process of what is commonly called a punchthrough IGBT using a thick wafer, which was employed before the invention of the wafer thinning technique, is as follows. An IGBT is formed by inputting, to a manufacturing process, a thick wafer in which an optimum-designed low-resistivity n-type layer and high-resistivity n− drift layer are epitaxially grown in advance on a low-resistivity p+ silicon substrate of 300 to 500 μm in thickness. In this method, the impurity concentrations and the thicknesses of the low-resistivity n-type layer and the high-resistivity n− drift layer are optimum-designed in advance and the thickness of the wafer (low-resistivity p+ silicon substrate) is as sufficiently large as 300 to 500 μm. Therefore, there is almost no probability that the wafer is broken during a device formation process and hence productivity using this process is high.
However, since the impurity concentration of the low-resistivity p+ silicon substrate is high and its thickness is too large, the minority carrier injection efficiency during an IGBT operation is very high. For example, it is known that an IGBT formed by this process is much worse in the on-voltage vs. turn-off loss characteristic etc. than an IGBT formed by the wafer thinning process even if such electrical characteristics as the turn-off characteristic are adjusted by a lifetime control process.
To solve this problem, in the above thick wafer process, a method has been proposed in which a low-resistivity p+ silicon substrate is ground from the back side at a final stage of the process to reduce its thickness to such an extent that it becomes a p-type collector layer of about 1 μm in thickness, and the minority carrier injection efficiency becomes low whereby the on-voltage vs. turn-off loss characteristic is improved (Tomoko Matsudai et al., “Advanced 60 μm Thin 600V Punch-through IGBT Concept for Extremely Low Forward Voltage and Low Turn-off Loss,” IEEE ISPSD 2001, pp. 441-444).
Furthermore, the following technique is described in JP-A-2002-76326 (abstract and paragraph 0026), in which a semiconductor functional portion is formed on one surface of a bonded semiconductor substrate. As for the other surface, whereas an outermost peripheral portion of each semiconductor chip is left in a frame form, the central portion is etched away to form a recess in such a manner that the thickness of the bottom portion of the recess is reduced to a limit value that secures necessary semiconductor characteristics. The recess is filled with a metal. In this manner, a semiconductor device having a low switching loss is formed while a manufacturing process using a thick, large-diameter semiconductor substrate is executed. Also disclosed are methods for detecting an etching end point in etching the back side of the semiconductor substrate in a frame form. In one method, an etching method is employed in which a substrate obtained by bonding semiconductor substrates having different crystal face orientations is used and etching anisotropy is provided because of the different crystal face orientations. Etching is performed at a correct depth from the back surface to the bonding boundary. In another method, an etching method is employed in which an insulating film is formed at the bonding boundary and used as an etching end point sensor.
Still further, a vertical MOSFET is known which has a trench gate structure and a trench drain opposed to it (See Japanese Patent No. 3,957,638). Trench gate bottoms and a semiconductor substrate that faces the trench gate bottoms are insulated from each other by an oxide film and trench drains penetrate through the oxide film and are in contact with the semiconductor substrate.
However, in the thick wafer grinding method of Matsudai et al., since the wafer grinding accuracy is usually about ±5 μm, the p-type collector layer may be lost entirely by excessive grinding when it is formed by grinding the thick, low-resistivity p+ silicon substrate in a final step so as to leave a 1-μm-thick layer. In this case, the on-voltage becomes very high. Conversely, if a p-type collector layer that is thicker than the design value 1 μm is left, a drawback arises that the loss characteristics vary to a very large extent as exemplified by a large turn-off loss. Furthermore, in the thick wafer grinding method of Matsudai et al., the thickness of a ground wafer is 60 to 70 μm. Therefore, as in the wafer thinning technique of Laska et al., there is a drawback that a wafer may be broken in steps that follow the step of thinning the wafer, such as a back surface electrodes forming step. As such, the thick wafer grinding method of Matsudai et al. has not been put into practical use yet.
That is, in the wafer thinning technique of Laska et al., an optimum design value of the thickness of the p-type collector layer can be attained more reliably than in the thick wafer grinding method of Matsudai et al. but a wafer is prone to be broken during a process (i.e., the productivity is low). In the thick wafer grinding method of Matsudai et al., optimum design values of the impurity concentration of the p-type collector layer and the impurity concentration and the thickness of the low-resistivity n-type layer can be realized and the productivity in terms of a low likelihood of wafer breakage during a process is high. However, it has a problem that device characteristics are made very bad due to thickness variation of the p-type collector layer.